Today boundary scan design in integrated circuits (ICs) is based on an IEEE standard referred to as 1149.1. In the future, boundary scan may be based on alternate IEEE boundary scan standards such as the currently developing P1149.2 standard. In boundary scan, flip flops and/or latches, referred to from this point forward as memories, and multiplexers form boundary scan cells at the IC input, output and bi-directional pins. The cells are serially connected and can be accessed by a test access port on the IC to provide controllability and observability of each IC pin type. Using the boundary scan structure within the IC, wiring interconnects and/or external circuitry located between ICs on a board or multichip module can be easily tested for assembly related faults such as shorts and opens. Boundary scan is well known in the electronics test industry.
In FIG. 1, an example 1149.1 bi-directional scan cell (BSC) is shown residing between an ICs functional core logic (FCL) and an input/output (I/O) pin. In this and all following Figures the IC functional circuitry areas are shown shaded to differentiate them from the IC test circuitry areas. The BSC 11 comprises three individual unidirectional scan cells (USC) 13, 15 and 17. One USC 13 resides in the 3-state control path between the FCL and the 3-state output buffer (3SOB), another USC 15 resides in the data output path between the FCL and 3SOB, and the other USC 17 resides in the data input path between the FCL and the input buffer IB. Each USC comprises dedicated test circuitry to implement multiplexers Mux1 and Mux2, and memories Mem1 and Mem2. Mux1 and Mem1 form the input section of each USC and are used to capture IC data (control in USC 13, output in USC 15, input in USC 17) and shift data through the serially connected USCs from their serial input (SI) to their serial output (SO). Mux2 and Mem2 form the output section of each USC and are used to output either IC data (control, output, input) or test data stored in Mem2.
In normal IC operation, IC data (control, output, input from FCL) is output from Mux2. During test operation, test data stored in Mem2 is output from Mux2. In normal IC operation, the input section of the USCs can be operated to capture IC data (control, output, input from FCL) and shift this data through Mem1 while Mux2 outputs this data. In test operation, the input section of the USCs can be operated to capture IC data (from FCL) and shift this data through Metal while Mux2 outputs test data from Mem2. The data resident in Mem1 after the shifting process is completed is updated into Mem2. Thus in test operation, the data output from Mux2 only changes at the end of the shifting process. The combination of the three USCs in FIG. 1 provide the 1149.1 test circuitry for BSCs located at bi-directional IC pins. The structure and operation of this 1149.1 BSC test circuitry is well known in the art.
In a bussed arrangement of I/O pins (for example, a bi-directional data bus), one control USC 13 can be used to enable or disable all bussed 3SOBs (as indicated by the dotted line from Mux2 of the control USC 13). Note that Mux2 of input USC 17 inhibits the input buffer from driving the FCL directly, and therefore the addition of a hi-drive buffer is typically required on the input path between the USC 17 and FCL as shown in FIG. 1. Including the hi-drive buffer adds test circuitry overhead to each I/O pin and delays the input signal from the I/O pin.
The full featured BSC of FIG. 1 is a required implementation on all pins of user programmable technologies that implement the 1149.1 test standard. Programmable technologies such as fuse programmable gate arrays, Ram programmable gate arrays, programmable crossbar switches, PALS, and ASIC gate arrays must anticipate the user programming each pin to be any one of an input, a 2-state output, a 3-state output, or an I/O pin type. Furthermore, in these programmable technologies, each pin requires its own control USC to allow individual 3-state control of each pin (i.e. one control USC cannot be used to control a bussed arrangement of I/O pins, as previously mentioned, since the pins must be completely programmable by the user). Unlike custom technologies, where IC pins can be optimized to contain only test circuitry for use with an input, output, or I/O pin, programmable technologies must include full I/O test circuitry on each pin so that the user can program the pins as required. This causes programmable technologies to have excess test circuitry on pins that are not programmed to be full I/O types. For example, if the IC of FIG. 1 was a programmable type and the pin was specified to be an input, not an I/O as shown, the control USC 13, the output USC 15, and the 3SOB would be unused circuitry. If the pin were programmed to be a 2-state output, the control USC 13, the input USC 17, the input buffer (IB), and the hi-drive input buffer would be excess circuitry. Only when the pin is programmed as an I/O type will all the test and functional circuitry of FIG. 1 be fully utilized.
In FIG. 2, another example 1149.1 BSC 21 is shown residing between the ICs FCL and I/O pin. This BSC is similar to the one in FIG. 1 except that it does not include an input USC. This BSC type provides full output test controllability and observability as described in the BSC 11 of FIG. 1, but only provides input test observability, not controllabiIity. The test input observability is made possible by feeding the input buffer's output into an additional input of Mux1 of the output USC 15A. The input from the input buffer also feeds directly into the FCL. Thus with the BSC of FIG. 2, it is not possible to control the input to the FCL during test operation as seen in the BSC of FIG. 1. This type of 1149.1 BSC is used on I/O pins when only external testing (IC to IC interconnect testing) is desired. The BSC of FIG. 2 is not advantageous for programmable technologies since it does not provide the user with full pin test programming control, i.e. it does not provide the user with the option of an input test capability (since it has no test input controllability) as does the BSC of FIG. 1. Therefore, the BSC of FIG. 2 is useful mainly in custom IC designs.
In FIG. 3, an example P1149.2 BSC 31 is shown residing between the FCL and I/O pin. This BSC is similar to the BSC of FIG. 1 in that it provides full input and output test controllability and observability of I/O pins. The difference between the existing 1149.1 and developing P1149.2 boundary scan standards is that the P1149.2 standard allows the capture/shift memories (Metals) of the boundary scan cells to be shared between test and functional operation. For example, in FIG. 3 the Metals (shaded to indicate functional circuitry) in the control, output, and input paths are functionally required components of the IC's I/O structure. If boundary scan was not implemented in the IC, the Mem1s would be directly wired between the FCL and input and 3-state output buffers. However, when P1149.2 boundary scan is included in the IC, as shown in FIG. 3, the functional Mem1s serve as the capture/shift memory for the control, output, and input USCs 33, 35 and 37, respectively. The dedicated test circuitry of each control, output, and input USC is shown non-shaded, to contrast against the shaded shared Mem1s which are part of the IC's functional circuitry.
In normal IC operation, the Mem1s of the P1149.2 USCs of FIG. 3 are used to register functional control, output, and input signals associated with normal I/O operation. During normal IC operation, functional control from the FCL passes through the control USC's Mux1, Mem1 and Mux2 to be input to the 3SOB, functional output from the FCL passes through the output USC's Mux1, Mem1 and Mux2 to be input to the 3SOB, and functional input from the I/O pin passes through the input buffer, the input USC's Mux1, Mem1 and Mux2, and the hi-drive buffer to be input to the FCL. Since the Mem1s of the P1149.2 BSC of FIG. 3 are used functionally, it is not possible to shift data through them while the IC is in normal operation mode, as can be done using the Mem1s of FIG. 1 which are dedicated test circuitry.
It should be noted that the hi-drive buffer is shaded (functional circuitry) in FIG. 3 because Mem1 is always interposed between IB and FCL, thus preventing IB from driving FCL directly, and typically requiring a hi-drive buffer even without any test circuitry.
In test operation, the Mem1s of the P1149.2 USCs of FIG. 3 are used to register test control, output, and input signals associated with test I/O operation. During test operation, test control from control Mem1 passes through the control USC's Mem2 and Mux2 to be input to the 3SOB, test output from output Metal passes through the output USC's Mem2 and Mux2 to be input to the 3SOB, and test input from input Mem1 passes through the input USC's Mem2 and Mux2 to be input to the FCL. During test operation, the capture/shift operation of Mux1 and Mem1, and the update operation of Mux2 and Mem2 is the same as described in the BSC of FIG. 1.
Because the Mem1s of the P1149.2 BSC of FIG. 3 cannot be shifted during normal IC operation, there is no way to shift in and update known test data into the Mem2s of the USCs before switching from functional to test operation, i.e. when Mux2 switches from outputting data from Mem1 (functional operation) to outputting data from Mem2 (test operation). Therefore the P1149.2 BSC will initially output unknown test data when the IC switches from functional to test operation. So while the P1149.2 BSC reduces the test logic overhead by the sharing of Metal for test and functional operation, the results are that the P1149.2 BSC enters test mode without knowing the state of the I/O pin, which can cause voltage contention between connected IC pins until test data is shifted in and updated from the BSC to the pins. This BSC of FIG. 3, like the BSC of FIG. 1, can be used in programmable technologies since it provides full input and output test controllability and observability. However, unlike the BSC of FIG. 1, the BSC of FIG. 3 does not provide for entry into test operation with known data in Mem2, which results in an unknown state at the I/O pin until a shift in and update operation is performed.
In FIG. 4, another example P1149.2 BSC 41 is shown residing between the FCL and I/O pin. This BSC is similar to the BSC of FIG. 2 in that it does not include an input USC and input observability is provided by an added input on Mux1 of the output USC 35A. Also the BSC of FIG. 4 is similar to the BSC of FIG. 3 in that it shares Metals between functional and test operations. Like the BSC of FIG. 2, this P1149.2 BSC is used on I/O pins when only external testing (IC to IC pin interconnect testing) is desired. Also like the BSC of FIG. 2, the BSC of FIG. 4 is not advantageous for programmable technologies since it does not provide the user with full pin test programming control (no test input controllability). Like the BSC of FIG. 3, the BSC of FIG. 4 enters test operation with unknown data in Mem2 and therefore the state of the I/O pin is unknown until the first shift in and update operation is performed.
FIG. 4 includes a functional input memory FIM (shaded as functional circuitry) at the IB output because the functionality of the IC requires the input data to be registered, as mentioned with respect to FIG. 3. The FIM of FIG. 4 is the same memory circuit as the Mem1 of USC 37 in FIG. 3, but is not shared with the BSC 41 of FIG. 4 and thus does not perform the Mem1 function illustrated in FIG. 3. The hi-drive buffer of FIG. 4 is shaded as functional circuitry because IB does not directly drive FCL, the same as in FIG. 3.
The dashed lines in FIGS. 1-4 represent optional connections between the USC outputs and Mux1s, thus permitting the USC output to be captured in Mem1 and shifted out for purposes of testing the USC itself.
In view of the foregoing, it is desirable to provide bi-directional scan cells with less test circuitry and to reduce the amount of unused circuitry when pins in programmable technologies are not programmed as I/O pins.
It is also desirable to avoid potential voltage contention problems due to the existence of unknown test data at IC pins upon initially switching into test operation in scan cells that share the Metal between functional and test operations.
It is further desirable to provide a bi-directional scan cell which permits input controllability without requiring a hi-drive buffer for FCL inputs.
The present invention provides a bi-directional scan cell design which implements the prior art Mem2 and Mux2 functions with less test circuitry than the prior art, provides input controllability without requiring a hi-drive buffer for FCL inputs, and includes an output latch circuit that resolves voltage contention at the IC pin. The invention also provides another low overhead scan cell output latch design which utilizes bus holder circuitry.